差分信號知識講座

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1、Click to edit Master title style,Click to edit Master text styles,Second level,Third level,Fourth level,Fifth level,12/4/2002,69,Differential Signaling,Introduction,Reading Chapter 6,12/4/2002,Agenda,Differential Signaling Definition,Voltage Parameters,Common mode parameters,Differential mode parame

2、ters,Current mode logic (CML) buffer,Relate to parameters,Modeling & simulation,Timing parameters,Clock recovery,Embedded clock,AC coupling,Common mode response,Issues with simulation,8B10B encoding,DC balanced codes,Duty Cycle distortion,Cycle,12/4/2002,Single Ended Signaling,All electrical signal

3、circuits require a loop or return path.,Single ended signal subject several means of distortions and noise.,Ground or reference may move due to switching currents (SSO noise). We touched on this in the ground conundrum class.,A single ended receiver only cares about a voltage that is referenced to i

4、ts own ground.,Electromagnetic interference can impose voltage on a single ended signal.,Signal passing from one board to another are subject to the local ground disturbance.,We can counteract many of these effect by adding more ground.,As frequencies increase beyond 1GHz, 80% of the signal will be

5、lost.,12/4/2002,Review of threshold sensitivity,The wave is referenced to either Vcc or Vss. Consequently the effective DC value of the wave will be tied to one of these rails.,The wave is attenuated around the effective DC component of the waveform, but the reference does not change accordingly. He

6、nce the clock trigger point between various clock load points is very sensitive to distortion and attenuation.,Tx,Vss,Vref,Vss,Rx2,Vref,Long line,Vss,Rx1,Vref,Short line,12/4/2002,Differential Signaling,Any signal can be considered a loop is completed by two wires.,One of the “wires” in single ended

7、 signaling is the “ground plane”,Differential signaling uses two conductors,The transmitter translates the single input signal into a pair,of outputs that are driven 180 out of phase.,The receiver, a differential amplifier, recovers the signal as the difference in the voltages on the two lines.,Adva

8、ntages of differential signaling can be summed up as follows,Differential Signaling is not sensitive to SSO noise.,A differential receiver is tolerant of its ground moving around.,If each “wire” of pair is on close proximity of one and other. electromagnetic interference imposes the same voltage on

9、both signals. The difference cancels out the effect.,Since the AC currents in the “wires” are equal but opposite and proximal, radiated EMI is reduced.,Signals passing from one board to another are not subject to the local ground disturbances.,As frequencies increase beyond 1GHz, up to 80% of the si

10、gnal may be lost, but difference still crosses 0 volts.,There are still loss issues for differential signaling but only come into play in high loss system. Most single ended systems assume approximately 15% channel loss.,12/4/2002,Differential Signaling - Cons,The cost is doubling the signal wires,

11、but this may not be so bad as compared to adding grounds to improve single ended signaling.,Routing constraint: Pair signals need to be routed together.,Differential signal have certain symmetry requirements that may pose routing challenges.,12/4/2002,Differential Signal Parameters,Voltage on line 1

12、 = a,Voltage on line 2 = b,Differential voltage d = a-b,Common mode voltage c= (a+b)/2,Odd mode signal, o = (a-b)/2,Even mode signal, e = (a+b)/2,Signal on line 1 a = e+o,Signal on line 2 b = e-o,Useful relations; o = b/2; e = c,Line 1,Line 2,Reference,12/4/2002,Propagation Terms to Consider,Differe

13、ntial mode propagation,Common mode propagation,Single ended mode (uncoupled) propagation,This is when the other line is not driven but terminated to absorbed reflections.,Transmission line matrixes will reflect these modes.,12/4/2002,Differential Microstrip Example,SE: single ended = uncoupled,12/4/

14、2002,Differential Impedance,Coupling between lines in a pair always decreases differential impedance,Differential impedance is always less that 2 times the uncoupled impedance,Differential impedance of uncoupled lines is 2 times the uncoupled impedance.,12/4/2002,Propagation Velocities,For TEM struc

15、tures, (striplines),Differential mode, Common Mode, and single ended velocities are the same,For Non TEM and Quasi-TEM structures (microstrip),Differential mode, Common Mode, and single ended velocities and impedances are not the same.,Common mode can be converted to differential mode at a receiver

16、and result in a differential signal disturbance.,12/4/2002,Example of Common Mode,Line 1 and line 2 have the same DC offset.,This is,DC common mode,.,It can be defined as an average DC for time duration of many UI cycles value as well.,Line1 and line 2 have the same AC offset,This is,AC common mode,

17、AC common mode,also result from time differences (skew) between signal on line 1 and line 2. This can result in AC common mode and differential signal loss.,The following slide will be used to clarify the above,12/4/2002,Differential Signaling Basics,For long channels, at GHz frequencies, signal ten

18、d look like sine waves.,The artificial offset common to line 1 and 2 has an average of 1 and varies around that average by +/-0.1 in a period manor.,12/4/2002,Individual signals,Devices need to have enough common mode dynamic voltage range to receive or transmit the waveforms. In this case the signa

19、ls swing between -0.1 and 2.1.,The sine wave amplitude is 1 and peak to peak is 2.,Signal a and b is what would be observed with 2 oscilloscope probes,12/4/2002,Differential Mode Signal,The differential amplitude is 2 and peak to peak is 4 which is 2 times the individual signal peak to peak amplitud

20、e.,Notice the distortions are gone.,12/4/2002,Common Mode Signal,The DC common mode signal is 1,The AC common mode signal is .2 v peak to peak,Some may specifications may call this 0.1 v peak from the DC average,We will add this common mode to the signals “a” and “b”,12/4/2002,Add,150 ps,skew to sig

21、nal b,Waveforms do not look so good.,We even have what appears to be non-monotonic behavior.,12/4/2002,Differential signal looks OK,However we lost differential signal amplitude.,It used to be 4 peak to peak and now is 3.562.,12/4/2002,Common mode measurements are different,Average is still 1. Peak

22、to peak is 0.944 but peak is 0.504,AC common mode signals can be converted to differential,12/4/2002,PWB structures that introduce Skew,An escape from a BGA or connector pinsintroduces skew,This is an example of skew compensation,12/4/2002,Bends introduce skew,Back to back bendscompensate for skew f

23、rom frequencies below 2 GHz.,Back to back bendscompensate for skew from frequencies below 2 GHz.,12/4/2002,More Terms: Balanced and Unbalanced,Good Agilent Technologies article on balance and unbalanced signaling, signaling in reference to ground,Balanced signaling is referenced only to the other po

24、rt terminal.,If each channel is identical, then this suggests a virtual AC ground between the two terminals. It is often useful to allow this AC ground to be a DC voltage to biasing devices.,12/4/2002,Ethernet 10/100BASE-T example,50,W,50,W,50,W,50,W,Transformer,Filter,Common-mode choke,Unbalanced,B

25、alanced,12/4/2002,Low Voltage Differential Signaling: LVDS,200,MHz 500 MHz Range,Published by IEEE in 1995,Lacks robustness for GHz Signaling,Well suite distributing system clocks,Good noise margin,Common mode impedance has wide range provide buffer design flexibility,Differential impedance is optim

26、ize around 100,W,Differential receiver switching thresholds are tighter than for single ended logic.,Most device require external termination and bias resistors,Does not have capacitance or package spec. This severely limits GHz operation,12/4/2002,Current Mode Logic,Emerging technology,No real spec

27、 yet but can infer operation from specs like PCI Express , Infiniband, USB, SATA, etc.,Tx and Rx lines are separate,The Tx driver steers current between the differential terminals,AC coupling between Tx and Rx with a series capacitor provides common mode design flexibility,Termination is in buffers.

28、 This may require compensation or a band gap reference to insure a tight resistance range.,12/4/2002,Example of,Simple,CML Differential Behavioral Circuit,Vcc,Vss,I_source,r_termn,C_term,r_termp,C_term,Positive Terminal,Negative Terminal,This exponent determines wave shape,This switch time offset,Ba

29、lance between for FET switch,2,nd,lecture,12/4/2002,Example of Sensitivities: I, balance, C,Vcc,I_source,More prominent for faster edges,12/4/2002,Example of Sensitivities: Slew, Skew, R,Vcc,I_source,+/skew,R/F slew,12/4/2002,Serial Differential,GHz transmission will have many UIs of data in transit

30、 on the interconnect at any points in time.,Hence it becomes useful to think of this as serial data transmission.,Often multiple single channels are ganged in parallel to achieve even higher data throughput.,12/4/2002,AC coupling issues,Series capacitors can build up charge difference between differ

31、ential terminals for the following reasons.,Unequal numbers off zero and ones,Duty cycle (UI) distortion.,The solution is to use a data code that is “DC” balanced.,8B10B (8 bit 10 bit) with disparity is one such code,Tight UI control is a basic requirement for keeping the signal eye open,12/4/2002,E

32、ye Diagram,The eye diagram is a convenient way to represent what a receiver will see as well as specifying characteristics of a transmitter.,The eye diagram maps all UI intervals on top of one and other.,The opening in eye diagram is measure of signal quality.,This is the simplest type of eye diagra

33、m. The are other form which we will discuss later,Eye Diagram,12/4/2002,Creating eye diagram,Plot periodic voltage time ramps (saw tooth waves) on x verses the voltage wave on Y.,Can be done with Avanwaves expression calculator and can be saved in a configuration file.,12/4/2002,Create ramp with exp

34、ression builder,Start of relative eye position,Time of eye start,Unit Interval,12/4/2002,Copy Ramp to X Axis,Use middle button to drag ramp to Current X-Axis,12/4/2002,Voltage and period volt-time ramp,12/4/2002,Clocking,The one thing omitted in the suggests in the previous slides on eye diagrams wa

35、s the “chop” frequency.,We assumed it was UI. This is simple for simulation. Time marches along and all signals start out synchronized in time. This is not true for real measurement since edges will significantly jitter and make it difficult to determinate where the exact UI is positioned.,Presently

36、, there are basically two forms of GHz+ clocking,Embedded clocking,Forwarded clocking,12/4/2002,Embedded clocking,This what is used in Fiber Channel, Gigabit Ethernet, PCI Express, Infiniband, SATA, USB, etc.,The clock is extracted from the data,There is requirement that data transitions are at a mi

37、nimum rate. 8B/10B guarantees this. We discuss this in more detail later.,A phase interpolator is normally used to extract the clock from the data. We discussed the phase interpolator in the clocking class. The phase interpolator is tied to the PCI Express-like jitter spec: Median and Jitter outlier

38、.,12/4/2002,Jitter Median and Outlier Spec,Eye opening is defined from a stable UI.,Jitter median used to determine a stable UI,It is used as a reference to determine eye opening,Jitter Outlier is used to guarantee limits of operation,Jitter Median,Jitter outlier,Eye diagram,UI,12/4/2002,Forwarded C

39、locking,The Tx clock is sourced and received down stream. The clock is a Tx data buffer synchronized with the Tx data bits.,A synchronization or training sequence on a data line is used to adjust the receiver clock so that it is in phase synchronization with the data.,The caveat is that the actual d

40、ata clock lags the real data by a few cycles.,The whole idea is that the jitter introduced over these cycles would be smaller than the jitter associated with two the PLLs used to provide base clocks for an embedded clock design.,12/4/2002,Aspects of AC coupling,We will explore issues with AC couplin

41、g with a simulation example.,First we will create a simple CML differential model,Next we will tie it to a differential transmission line and a terminator.,Assignment 7,is to reproduce these effects with a HSPICE program. The output Avanwaves with a power point story summary what you will hand in.,T

42、he basis for our work will be last semesters testckt.sp deck,12/4/2002,Behavioral Data Model Example,12 bit of repeating data,010101 001001 v(t) data,UI = 500 psTr=Tf=100ps,Rterm=50,Cterm=0.25pf,Vswing = 800 mV,I=Vswing/(50|50)/2,Wave shape*,*,Refer to first course,3,rd,lecture,12/4/2002,AC coupled

43、Differential Circuit,AC coupling caps are normally larger, but are scaled down to illustrate common mode effects,12/4/2002,Top Level HSPICE CODE,Modified,Convenience,12/4/2002,No initial conditions on DC blocking caps,300,ns of simulation time!,Cblkn pkg2_nb pkg2_n 1nf $ic=400mv,Cblkp pkg2_pb pkg2_p

44、 1nf $ic=400mv,101010 101010 repeating 12 bit pattern,Differential,Single ended,Reproduce this at package 2 (receiver),12/4/2002,Set IC to Vswing/2,Differential,Single ended,Reproduce this at package 2 (receiver),12/4/2002,Not completely fixed,Initial voltage for D+ and D+ is not 0 so there is a ste

45、p response when the wave reaches the receiver.,We can fix this by multiplying both “n” and “p” control waves for the VCR (voltage controlled resistor) by 0 for the first cycle.,This forces the DC solution at the other end of the line to 0 volts differential.,12/4/2002,Insure both legs start at same

46、voltage,Qualifying voltage,Qualifying voltagep control voltage,Qualifying voltagen control voltage,12/4/2002,Results Pretty good,Differential,Single ended,Reproduce this at package 2 (receiver),May have to ignore first 1-2 cycles,12/4/2002,Now lets change bit pattern,100000001010,The pattern creates

47、 a DC charge to be built up in the cap,The solution is to create a code that has equal amount of 1s and zeros. This is the rational for 8bit 10 bit (8b10b) coding,Differential,Single ended,Reproduce this at package 2 (receiver),12/4/2002,Crossing Offset,The crossing offset is the horizontal line tha

48、t is in the vertical center of the eye and it should be at 0 volts for a differential signal.,The amount of offset is the average DC value. A simple approximation is one minus the ratio of ones to zeros times the received vswing/2.,This does not included edge shape effects,12/4/2002,Repeat patterns

49、of 5 ones and 6 zeros,Approx. offset,Reproduce this at package 2 (receiver),Hint: start eye diagram at 200 ns,12/4/2002,8,b/10b encoding and background,Courtesy of Scott Gardiner, Intel,12/4/2002,8,b/10b - Simple Scheme,The encoding is comprehended in a set of tables which conform to a set of predet

50、ermined “rules”,Helpful Hint: Complete tables that give all the literal 10b encodings do exist- and they comprehend all of the encoding rules,8 bits are encoded into 10 bits,12/4/2002,8,b/10b: Overview,The 10 bits are referred to as a “symbol” or a “code-group:”,The original 8 bits are broken into a

51、 3 bit block and a 5 bit block (each of these are called sub-blocks),F,1,111,1,0001,The 3 bit sub-block (labeled HGF) is encoded into 4 new bits (labeled fghj) & the 5 bit sub-block (EDCBA) is encoded into 6 new bits (abcdei),HGFEDCBA,notation commonly represents the un-encoded bits, and,abcde,i,fgh

52、,j,represents the encoded bits; note that the relative order and position of the sub-blocks is switched upon encoding,HGF,EDCBA,abcde,i,fgh,j,Hence, an extra bit,j, is added to the newly encoded 3 bit block and an extra bit,i, to the encoded 4 bit block creating a 4 and 5 bit sub-blocks,12/4/2002,8,

53、b/10b Character Conventions,Both Data Characters and Special Control Characters exist; (nomenclature: D.a.b & K.a.b),D/K = Signifies Data or Control,a = 5 bit block to be encoded,b = 3 bit block to be encoded,Set of Available Data and Control Characters,Data (D.a.b),D0.0-D31.0, D0.1-D031.1, . D0.7 D

54、31.7,All 256 Possible 8-bit Data characters (00 through FF HEX),Control (K.a.b),K28.0 K28.7, K23.7, K27.7, K29.7, K30.7,12/4/2002,8,b/10b - DC balancing & Disparity,Never more than 5 consecutive 1s or 0s allowed in a row (consecutively).i.e. the maximum “run rate” is 5 to maintain a DC balanced tran

55、smission.,This guarantees the lowest frequency to be 1/10 of the max frequency. i.e. only 1 decade data bandwidth required.,With 8b/10b, either positive (RD+) or negative (RD-) disparity encoding is possible,12/4/2002,8,b/10b - Disparity,Disparity is “the difference between the number of ones and ze

56、ros.positive and negative disparity refer to an excess of ones or zeros respectively”.,Note: neutral disparity is said to occur when RD+ and RD- encoding are,identical-,meaning they will,each,have the,same number of ones and zeros (there are some exceptions),A given sub-block or symbol can have an a

57、ctual disparity number of either a zero (neutral), +2 or 2, though the Running Disparity is said only to be Positive, Negative or Neutral.,12/4/2002,8,b/10b Running Disparity,The Running or Current Disparity (a binary value of + or -) is tracked by the TX/RX and is computed at every sub-block bounda

58、ry and at each symbol boundary.,The value from one sub-block or symbol is used with that of the next sub-block or symbol to give a “running” or “current” status.,12/4/2002,8,b/10b Running Disparity Algorithm,For a given encoding of a byte, the starting disparity is what existed at the end of the pre

59、vious symbol,The running disparity is then calculated first for the,6 bit sub-block,comprehending the starting disparity value,;,The 6 bit sub block disparity value,is then used as the starting disparity when the running disparity calculated for the,4 bit sub-block,The running disparity for the enti

60、re 10 bit,symbol,is now the,same,as the running disparity found at the end of the,4 bit sub-block,(and the running disparity at the beginning of the next,symbol /,6 bit sub-block,is the,same,as that found at the end of the this,symbol,),Again, a given sub-block or symbol can have an actual disparity

61、 number of either a zero (neutral), +2 or 2, though the Running Disparity is only said to be Positive, Negative or Neutral.,12/4/2002,8,b/10b - Running Disparity Calculation Algorithm:,Assumptions:,The 8b to 10b encoding has already been done; A current disparity value is already assumed,Process:,Ca

62、lculate the disparity for the leftmost 6 bits first, keeping in mind the current disparity value before entering the algorithm. Then calculate the disparity for the rightmost 4 bits keeping in mind the disparity value determined after analyzing the previous 6 bits. The disparity for both the 6-bit a

63、nd the 4-bit blocks should be calculated as follows:,12/4/2002,8,b/10b - Running Disparity Calculation Method,Method:,If # of 1s 0s,Disparity = Positive (1),Else if # of 0s 1s,Disparity = Negative (0),Else if 6-bit = 000111,Then Disparity = Positive (1),Else if 6-bit = 111000,Then Disparity = Negati

64、ve (0),Else if 4-bit = 0011,Then Disparity = Positive (1),Else if 4-bit = 1100,Then Disparity = Negative (0),Else Disparity = Disparity,(if none of the above, then the disparity value doesnt change),Note:,Assuming a encoding, more 1s across the entire 10b code yields positive,disparity, more 0s yiel

65、ds negative disparity, and even #s of 1s and 0s yields neutral disparity,(i.e. disparity is the same as it was before).,12/4/2002,8,b/10b -,Disparity & Encoding Example:,Transmitter keeps running track of current disparity (it is either RD, RD+,or neutral),Neutral means the disparity tracker keeps the previous RD- or RD+ value,A Running Disparity of RD+ is always followed by an RD-